Open AccessMulticore Flow Processor with Wire‐Speed Flow Admission Control
Author(s) -
Doo KyeongHwan,
Yoon BinYeong,
Lee BhumCheol,
Lee SoonSeok,
Han Man Soo,
Kim WhanWoo
Publication year - 2012
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.12.1812.0046
Subject(s) - computer science , computer network , router , flow control (data) , network packet , network processor , packet processing , multi core processor , throughput , embedded system , operating system , wireless
We propose a flow admission control (FAC) for setting up a wire‐speed connection for new flows based on their negotiated bandwidth. It also terminates a flow that does not have a packet transmitted within a certain period determined by the users. The FAC can be used to provide a reliable transmission of user datagram and transmission control protocol applications. If the period of flows can be set to a short time period, we can monitor active flows that carry a packet over networks during the flow period. Such powerful flow management can also be applied to security systems to detect a denial‐of‐service attack. We implement a network processor called a flow management network processor (FMNP), which is the second generation of the device that supports FAC. It has forty reduced instruction set computer core processors optimized for packet processing. It is fabricated in 65‐nm CMOS technology and has a 40‐Gbps process performance. We prove that a flow router equipped with an FMNP is better than legacy systems in terms of throughput and packet loss.