Open AccessAsynchronous 2‐Phase Protocol Based on Ternary Encoding for On‐Chip Interconnect
Author(s) -
Oh MyeongHoon,
Kim Seongwoon
Publication year - 2011
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.11.0211.0063
Subject(s) - handshake , asynchronous communication , interconnection , chip , computer science , encoding (memory) , encoder , cmos , protocol (science) , throughput , electronic circuit , electronic engineering , ternary operation , reduction (mathematics) , electrical engineering , engineering , computer network , mathematics , telecommunications , medicine , alternative medicine , geometry , pathology , artificial intelligence , wireless , programming language , operating system
Level‐encoded dual‐rail (LEDR) has been widely used in on‐chip asynchronous interconnects supporting a 2‐phase handshake protocol. However, it inevitably requires 2N wires for N‐bit data transfers. Encoder and decoder circuits that perform an asynchronous 2‐phase handshake protocol with only N wires for N‐bit data transfers are presented for on‐chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current‐mode multiple valued logics. Using 0.25 μm CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power‐delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.