Open AccessLow‐Power, All Digital Phase‐Locked Loop with a Wide‐Range, High Resolution TDC
Author(s) -
Pu YoungGun,
Park AnSoo,
Park JoonSung,
Lee KangYoon
Publication year - 2011
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.11.0110.0295
Subject(s) - digitally controlled oscillator , phase locked loop , phase noise , cmos , time to digital converter , dbc , inductor , amplifier , electronic engineering , transconductance , materials science , voltage , electrical engineering , engineering , transistor , jitter , variable frequency oscillator , clock signal
In this paper, we propose a low‐power all‐digital phase‐ locked loop (ADPLL) with a wide input range and a high resolution time‐to‐digital converter (TDC). The resolution of the proposed TDC is improved by using a phase‐interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm 2 using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is ‐120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.