Open AccessEdge‐Preserving Algorithm for Block Artifact Reduction and Its Pipelined Architecture
Author(s) -
Vinh Truong Quang,
Kim YoungChul
Publication year - 2010
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.10.0109.0290
Subject(s) - deblocking filter , computer science , very large scale integration , block (permutation group theory) , field programmable gate array , algorithm , enhanced data rates for gsm evolution , reduction (mathematics) , pixel , filter (signal processing) , artificial intelligence , computer hardware , computer vision , embedded system , mathematics , geometry
This paper presents a new edge‐protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge‐protection maps. Based on these maps, a two‐step adaptive filter which includes offset filtering and edge‐preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory‐reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 µm CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.