Open AccessEffects of Interfacial Dielectric Layers on the Electrical Performance of Top‐Gate In‐Ga‐Zn‐Oxide Thin‐Film Transistors
Author(s) -
Cheong WooSeok,
Lee JeongMin,
Lee JongHo,
Park SangHee Ko,
Yoon Sung Min,
Byun ChunWon,
Yang Shinhyuk,
Chung Sung Mook,
Cho Kyoung Ik,
Hwang ChiSun
Publication year - 2009
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.09.1209.0049
Subject(s) - thin film transistor , materials science , dielectric , optoelectronics , transistor , oxide , threshold voltage , gate dielectric , high κ dielectric , annealing (glass) , stress (linguistics) , composite material , voltage , electrical engineering , metallurgy , layer (electronics) , engineering , linguistics , philosophy
We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top‐gate In‐Ga‐Zn‐oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si 3 N 4 and Al 2 O 3 , the electrical properties are analyzed. After post‐annealing at 200°C for 1 hour in an O 2 ambient, the sub‐threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative‐bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si‐based broken bonds and hydrogen‐based bonds. From constant‐current stress tests of Id = 3 µA, an IGZO‐TFT with heat‐treated Si 3 N 4 IDL shows a good stability performance, which is attributed to the compensation effect of the original charge‐injection and electron‐trapping behavior.