Open AccessMapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture
Author(s) -
Wu ChiaMing,
Chi HsinChou,
Chang RuayShiung
Publication year - 2009
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.09.0108.0608
Subject(s) - network on a chip , circuit switching , latency (audio) , computer science , scheduling (production processes) , embedded system , architecture , network packet , chip , packet switching , electronic circuit , computer network , computer architecture , engineering , telecommunications , electrical engineering , art , operations management , visual arts
Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.