
A Novel Scalable and Storage‐Efficient Architecture for High Speed Exact String Matching
Author(s) -
Peiravi Ali,
Rahimzadeh Mohammad Javad
Publication year - 2009
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.09.0108.0353
Subject(s) - scalability , computer science , string (physics) , realization (probability) , string searching algorithm , filter (signal processing) , computer engineering , throughput , network packet , parallel computing , pattern matching , data structure , metric (unit) , algorithm , theoretical computer science , computer hardware , computer network , mathematics , engineering , artificial intelligence , telecommunications , statistics , database , programming language , mathematical physics , computer vision , wireless , operations management
String matching is a fundamental element of an important category of modern packet processing applications which involve scanning the content flowing through a network for thousands of strings at the line rate. To keep pace with high network speeds, specialized hardware‐based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings. In this paper, a novel architecture based upon a recently proposed data structure called the Bloomier filter is proposed which can successfully support scalability. The Bloomier filter is a compact data structure for encoding arbitrary functions, and it supports approximate evaluation queries. By eliminating the Bloomier filter's false positives in a space efficient way, a simple yet powerful exact string matching architecture is proposed that can handle several thousand strings at high rates and is amenable to on‐chip realization. The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions. The results show that the proposed approach achieves better performance compared to other existing architectures measured in terms of throughput per logic cells per character as a metric.