Open AccessA 40 Gb/s Clock and Data Recovery Module with Improved Phase‐Locked Loop Circuits
Author(s) -
Park Hyun,
Kim Kang Wook,
Lim SangKyu,
Ko Jesoo
Publication year - 2008
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.08.1107.0043
Subject(s) - phase locked loop , jitter , clock domain crossing , clock recovery , electronic engineering , computer science , delay locked loop , clock signal , pseudorandom binary sequence , phase detector , clock skew , lock (firearm) , data recovery , electronic circuit , synchronous circuit , computer hardware , binary number , engineering , electrical engineering , mathematics , voltage , mechanical engineering , arithmetic
A 40 Gb/s clock and data recovery (CDR) module for a fiber‐optic receiver with improved phase‐locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D‐type flip‐flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo‐random binary sequence (2 31 ‐1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D‐FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.