Open AccessRetina‐Motivated CMOS Vision Chip Based on Column Parallel Architecture and Switch‐Selective Resistive Network
Author(s) -
Kong JaeSung,
Hyun HyoYoung,
Seo SangHo,
Shin JangKyoo
Publication year - 2008
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.08.0108.0263
Subject(s) - chip , cmos , pixel , power consumption , enhanced data rates for gsm evolution , resistive touchscreen , electronic circuit , computer science , machine vision , power (physics) , electronic engineering , materials science , optoelectronics , engineering , electrical engineering , artificial intelligence , physics , quantum mechanics
A bio‐inspired vision chip for edge detection was fabricated using 0.35 μm double‐poly four‐metal complementary metal‐oxide‐semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of 160×120 pixels has been fabricated in 5×5 mm 2 silicon die. It shows less than 10 mW of power consumption.