Open AccessInterconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains
Author(s) -
Yi Hyunbean,
Song Jaehoon,
Park Sungju
Publication year - 2008
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.08.0107.0275
Subject(s) - boundary scan , controller (irrigation) , interconnection , benchmark (surveying) , fault (geology) , embedded system , engineering , computer science , electronic engineering , electrical engineering , integrated circuit , telecommunications , agronomy , geodesy , seismology , geology , geography , biology
This paper introduces an interconnect delay fault test (IDFT) controller on boards and system‐on‐chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.