Open AccessA New Scan Partition Scheme for Low‐Power Embedded Systems
Author(s) -
Kim HongSik,
Kim CheongGhil,
Kang Sungho
Publication year - 2008
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.08.0107.0092
Subject(s) - scan chain , dissipation , partition (number theory) , benchmark (surveying) , design for testing , computer science , power consumption , test compression , algorithm , electronic circuit , automatic test pattern generation , power (physics) , parallel computing , mathematics , integrated circuit , engineering , statistics , testability , electrical engineering , physics , geodesy , combinatorics , quantum mechanics , thermodynamics , geography , operating system
A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low‐power embedded systems. In scan‐based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph‐based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.