Open AccessFurther Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio
Author(s) -
Ituero Pablo,
LópezVallejo Marisa
Publication year - 2008
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.08.0107.0076
Subject(s) - computer science , very long instruction word , computer architecture , turbo code , software , software defined radio , operand , throughput , parallel computing , decoding methods , embedded system , computer hardware , wireless , operating system , algorithm , telecommunications
Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi‐standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual‐clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi‐operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance‐area trade‐off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.