Open AccessDesign and Implementation of Unified Hardware for 128‐Bit Block Ciphers ARIA and AES
Author(s) -
Koo Bonseok,
Ryu Gwonho,
Chang Taejoo,
Lee Sangjin
Publication year - 2007
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.07.0207.0077
Subject(s) - advanced encryption standard , block cipher , computer science , s box , embedded system , cryptography , permutation (music) , encryption , cipher , field programmable gate array , block (permutation group theory) , architecture , aes implementations , computer hardware , computer architecture , arithmetic , algorithm , computer network , mathematics , art , physics , geometry , acoustics , visual arts
ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area‐efficient unified hardware architecture of ARIA and AES. Both algorithms have 128‐bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128‐bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.