Open AccessA 9‐Bit 80‐MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique
Author(s) -
Lee SeungChul,
Jeon YoungDeuk,
Kwon JongKee
Publication year - 2007
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.07.0206.0180
Subject(s) - differential nonlinearity , integral nonlinearity , cmos , least significant bit , offset (computer science) , preamplifier , folding (dsp implementation) , linearity , electronic engineering , nonlinear system , computer science , 8 bit , computer hardware , voltage , electrical engineering , engineering , physics , amplifier , converters , quantum mechanics , programming language , operating system
A 9‐bit 80‐MS/s CMOS pipelined folding analog‐to‐digital converter employing offset‐canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc‐decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ×0.6 LSB and ×1.6 LSB, respectively.