Open AccessAn FPGA Implementation of High‐Speed Flexible 27‐Mbps 8‐StateTurbo Decoder
Author(s) -
Choi Duk Gun,
Kim MinHyuk,
Jeong Jin Hee,
Jung Ji Won,
Bae JongTae,
Choi SeokSoon,
Yun Young
Publication year - 2007
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.07.0106.0122
Subject(s) - computer science , decoding methods , turbo code , phase shift keying , turbo equalizer , field programmable gate array , algorithm , turbo , soft decision decoder , electronic engineering , computer hardware , concatenated error correction code , bit error rate , block code , engineering , automotive engineering
In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half‐rate turbo decoder designed for binary quadrature phase‐shift keying (B/QPSK) modulation. A transformation applied to the incoming I‐channel and Q‐channel symbols allows the use of an off‐the‐shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix‐4, dual‐path processing, parallel decoding, and early‐stop algorithms. We implement the proposed scheme on a field‐programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.