Open AccessDesign and Architecture of Low‐Latency High‐Speed Turbo Decoders
Author(s) -
Jung Ji Won,
Lee In Ki,
Choi Duk Gun,
Jeong Jin Hee,
Kim Ki Man,
Choi EunA,
Oh Deock Gil
Publication year - 2005
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.05.0905.0033
Subject(s) - computer science , interleaving , decoding methods , turbo equalizer , turbo code , turbo , latency (audio) , reduction (mathematics) , algorithm , low latency (capital markets) , real time computing , parallel computing , concatenated error correction code , block code , mathematics , engineering , computer network , telecommunications , geometry , automotive engineering , operating system
In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.