Open AccessAn Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder
Author(s) -
Suh Kibum,
Park Seongmo,
Cho Hanjin
Publication year - 2005
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.05.0905.0032
Subject(s) - macroblock , verilog , quantization (signal processing) , computer science , encoder , algorithm , hardware architecture , hadamard transform , inverse , transform coding , computer hardware , discrete cosine transform , mathematics , artificial intelligence , field programmable gate array , decoding methods , software , image (mathematics) , mathematical analysis , programming language , operating system , geometry
In this paper, we propose a novel hardware architecture for an intra‐prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing 4×4 Hadamard transform and quantization during 16×16 prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix 0.35 µm TLM (triple layer metal) library.