Open AccessPipelined Scheduling of Functional HW/SW Modules for Platform‐Based SoC Design
Author(s) -
Kim Wonjong,
Chang JuneYoung,
Cho Hanjin
Publication year - 2005
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.05.0905.0011
Subject(s) - computer science , embedded system , scheduling (production processes) , encoder , system on a chip , computer architecture , pipeline transport , architecture , dual layer , software , computer hardware , layer (electronics) , engineering , operating system , art , operations management , chemistry , organic chemistry , environmental engineering , visual arts
We developed a pipelined scheduling technique of functional hardware and software modules for platform‐based system‐on‐a‐chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32‐bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16‐bit single‐layer architecture.