Open AccessAC Modeling of the ggNMOS ESD Protection Device
Author(s) -
Choi JinYoung
Publication year - 2005
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.05.0104.0196
Subject(s) - parasitic extraction , nmos logic , low noise amplifier , electrical impedance , capacitor , electrical engineering , amplifier , noise (video) , electronic engineering , electrostatic discharge , impedance matching , equivalent circuit , materials science , engineering , computer science , transistor , cmos , voltage , artificial intelligence , image (mathematics)
From AC analysis results utilizing a 2‐dimensional device simulator, we extracted an AC‐equivalent circuit of a grounded‐gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.