Open AccessA 15 nm Ultra‐thin Body SOI CMOS Device' with Double Raised Source/Drain for 90 nm Analog Applications
Author(s) -
Park ChangHyun,
Oh MyungHwan,
Kang HeeSung,
Kang HoKyu
Publication year - 2004
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.04.0104.0074
Subject(s) - silicon on insulator , pmos logic , nmos logic , materials science , optoelectronics , transistor , ring oscillator , electrical engineering , cmos , contact resistance , static random access memory , silicon , voltage , nanotechnology , layer (electronics) , engineering
Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm 2 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.