Open AccessA Memory‐Efficient Block‐wise MAP Decoder Architecture
Author(s) -
Kim Sik,
Hwang SunYoung,
Kang Moon Jun
Publication year - 2004
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.04.0103.0091
Subject(s) - decoding methods , computer science , block (permutation group theory) , maximum a posteriori estimation , soft decision decoder , turbo code , bit error rate , turbo , algorithm , block size , throughput , turbo equalizer , error detection and correction , block error rate , block code , computer hardware , concatenated error correction code , mathematics , wireless , telecommunications , engineering , telecommunications link , maximum likelihood , statistics , geometry , computer security , key (lock) , automotive engineering
Next generation mobile communication system, such as IMT‐2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block‐wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit‐error rate (BER) performance of the block‐wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block‐wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.