Open AccessEfficient Test Data Compression and Low Power Scan Testing in SoCs
Author(s) -
Jung JunMo,
Chong JongWha
Publication year - 2003
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.03.0303.0017
Subject(s) - test compression , benchmark (surveying) , volume (thermodynamics) , power (physics) , scan chain , hamming code , test data , automatic test pattern generation , power consumption , design for testing , computer science , electronic circuit , data compression , hamming distance , computer hardware , algorithm , integrated circuit , engineering , reliability engineering , electrical engineering , decoding methods , block code , physics , testability , geodesy , quantum mechanics , geography , programming language , operating system
Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.