Open AccessAE32000B: a Fully Synthesizable 32‐Bit Embedded Microprocessor Core
Author(s) -
Kim HyunGyu,
Jung DaeYoung,
Jung HyunSup,
Choi YoungMin,
Han JungSu,
Min ByungGueon,
Oh HyeongCheol
Publication year - 2003
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.03.0303.0008
Subject(s) - computer science , microprocessor , coprocessor , embedded system , benchmark (surveying) , instructions per cycle , folding (dsp implementation) , instruction set , computer hardware , cmos , computer architecture , parallel computing , central processing unit , engineering , electronic engineering , electrical engineering , geodesy , geography
In this paper, we introduce a fully synthesizable 32‐bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35‐·m library and a 0.18‐·m library. With the 0.35‐·m library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18‐·m library.