Open AccessA Platform‐Based SoC Design of a 32‐Bit Smart Card
Author(s) -
Kim Wonjong,
Kim Seungchul,
Bae Younghwan,
Jun Sungik,
Park Youngsoo,
Cho Hanjin
Publication year - 2003
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.03.0103.0026
Subject(s) - smart card application protocol data unit , smart card , java card , computer science , embedded system , open smart card development platform , openpgp card , multos , computer hardware , cryptography , power consumption , interface (matter) , microprocessor , power (physics) , java , operating system , credit card , card security code , computer security , java applet , maximum bubble pressure method , world wide web , bubble , quantum mechanics , payment , physics
In this paper, we describe the development of a platform‐based SoC of a 32‐bit smart card. The smart card uses a 32‐bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 µm technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.