Open AccessChip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration
Author(s) -
John H. Lau,
Cheng-Ta Ko,
Chia-Yu Peng,
Kaiming Yang,
Tim Xia,
Puru Bruce Lin,
Jean-Jou Chen,
PoChun Huang,
Tzvy-Jang Tseng,
Eagle Lin,
Leo Chang,
Curry Lin,
Winnie Lu
Publication year - 2020
Publication title -
journal of microelectronics and electronic packaging
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.192
H-Index - 17
eISSN - 1555-8037
pISSN - 1551-4897
DOI - 10.4071/imaps.1137828
Subject(s) - fan out , chip , printed circuit board , reliability (semiconductor) , engineering , fabrication , integrated circuit , drop (telecommunication) , electronic engineering , integrated circuit packaging , electrical engineering , medicine , power (physics) , physics , alternative medicine , pathology , quantum mechanics
In this investigation, the chip-last, redistribution-layer (RDL)–first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10 × 10 mm2) and two small chips (7 × 5 mm2) by an FOPLP method on a 20 × 20-mm2 RDL-first substrate fabricated on a 515 × 510 mm2 temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a printed circuit board (PCB) is performed, and test results including failure analysis are presented. Some recommendations are also provided.