z-logo
open-access-imgOpen Access
High-Temperature Double-Layer Ceramic Packaging Substrates
Author(s) -
Ardalan Nasiri,
Simon S. Ang
Publication year - 2020
Publication title -
journal of microelectronics and electronic packaging
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.192
H-Index - 17
eISSN - 1555-8037
pISSN - 1551-4897
DOI - 10.4071/imaps.1123535
Subject(s) - materials science , ceramic , composite material , temperature cycling , electrical conductor , dielectric , leakage (economics) , insulator (electricity) , dielectric strength , thermal , optoelectronics , physics , meteorology , economics , macroeconomics
A double-layer ceramic electronic packaging technology that survives the Venusian surface temperature of 465°C was developed using a ceramic interlayer dielectric with gold conductors. A 60-μm ceramic interlayer dielectric served as the insulator between the top and bottom gold conductors on high-purity ceramic substrates. Test devices with AuPtPd metallization were attached to the top gold pads using a thick-film gold paste. Thermal aging for 115 h at 500°C and thermal cycling from room temperature to 450°C were performed. Dielectric leakage tests of the interlayer ceramic layer between the top and bottom gold conductors revealed a leakage current density of less than 50 × 10−7 A/cm2 at 600 V after thermal cycling. Gold conductor resistance increased slightly after thermal cycling. The die shear test showed a 33% decrease in die shear strength after thermal tests and its 6.16 kg-F die shear strength satisfies the Military Standard Product Testing Services (MIL-STD) method.

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here
Accelerating Research

Address

John Eccles House
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom