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FEASIBILITY STUDY OF 8-BIT MICROCONTROLLER APPLICATIONS FOR ETHERNET / AŠTUONIŲ SKILČIŲ MIKROVALDIKLIŲ PANAUDOJIMO GALIMYBIŲ TYRIMAS ETHERNET TINKLO ĮRENGINIUOSE
Author(s) -
Lech Gulbinovič
Publication year - 2011
Publication title -
mokslas - lietuvos ateitis
Language(s) - English
Resource type - Journals
eISSN - 2029-2341
pISSN - 2029-2252
DOI - 10.3846/mla.2011.017
Subject(s) - packet processing , computer science , ethernet , internet control message protocol , network packet , computer network , microcontroller , embedded system , processing delay , latency (audio) , computer hardware , real time computing , transmission delay , telecommunications

Feasibility study of 8-bit microcontroller applications for Ethernet is presented. Designed device is based on ATmega32 microcontroller and 10 Mbps Ethernet controller ENC28J60. Device is simulated as mass queuing theoretical model with ticket booking counter. Practical explorations are accomplished and characteristics are determined. Practical results are compared to theoretical ones. Program code and device packet processing speed optimization are discussed. Microcontroller packet processing speed and packet latency depend on packet size. For ICMP protocol packet processing speed varies 1.4–2.1 Mbps, latency – 0.8–8.4 ms. UDP protocol packet processing speed varies 1.3–1.8 Mbps, latency – 1.1–9.6 ms. Packet processing speed depends on compilation settings and program code compression level. Best results are reached on optimization le­vel ‑O3, then speed increased ~3% but program code size increased 68% comparing to –Os optimization level.

Article in Lithuanian

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