Open AccessComputing Performance Enhancement of VLIW Architecture Using Instruction Level Parallelism
Author(s) -
V. Venkata Nagendra Reddy,
A. Sudhakar,
P. Sivakumar
Publication year - 2020
Publication title -
international journal of innovative science and research technology
Language(s) - English
Resource type - Journals
ISSN - 2456-2165
DOI - 10.38124/ijisrt20sep241
Subject(s) - very long instruction word , computer science , operand , parallel computing , instruction set , architecture , computer architecture , register file , instruction level parallelism , processor register , parallelism (grammar) , computer hardware , memory address , semiconductor memory , art , visual arts
Our paper proposes the new method of processor architecture called as VLIW for enhancing the performance of the architecture. VLIW is the complexity architecture because the enormous number of registers, slices, flip flops, counters, operand, ALUs, and MUXs used. The VLIW has the fife stages of pipelines for executing the architecture are (1) fetching the 128-bit instruction memory, (2) decode stage or it is also called as the operands reading stage because the total number of operands are implemented in this stage, (3) execution stage, here the operations with the parallel executions units which has the four operations, (4) memory stage is used for loading or for storing the data from/to the memory and (5) write back stage in this stage the outputs of all the stage is collected and write back into the register file for storing the output values. The whole process of implementation is implemented in the FPGA of the family of Spartan-6 XC6SLX-3CSG324 device. In this proposed architecture the performance of the architecture is increased by reducing the time taken to execute the CPU of Xst completion of the architecture