Open AccessAccurate Estimation of Power Consumption for Binary Comparator System using Back Tracking
Author(s) -
Mangal Deep Gupta,
R. K. Chauhan
Publication year - 2021
Publication title -
ecti transactions on electrical eng. / electronics and communications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.148
H-Index - 7
ISSN - 1685-9545
DOI - 10.37936/ecti-eec.2021192.244122
Subject(s) - comparator , computer science , operand , schematic , logic gate , nand gate , binary number , adder , electronic engineering , electronic circuit , power (physics) , computer hardware , cmos , algorithm , engineering , electrical engineering , mathematics , arithmetic , voltage , physics , quantum mechanics
This paper presents a design of a binary comparator circuit using minimum fan-in logic gates (NAND-NOR) for achieving low power-delay-product (PDP). A 2-bit binary comparator circuit is re-designed to minimize fan-in of logic gates. Utilizing the concept of 2–bit comparator, a general gate-level architecture of a comparator system is proposed for higher input operands. A back-tracking model has been proposed in this work to estimate the worst-case performance in terms of delay and power or PDP for binary comparator circuits. It combines the advantages of the simulation-based method for power estimation and dynamic timing analysis (DTA) techniques for timing analysis. This work has also been extended for 20, 16, 14, 10, and 7-nm FINFET technology. The comparator circuits are simulated on Pyxis schematic tool by Mentor Graphics.