Open AccessCompact FPU Design and Embedding in a Ubiquitous Processor for Multimedia Performance Enhancement
Author(s) -
Masa-aki Fukase,
Tomoaki Sato
Publication year - 2007
Publication title -
ecti transactions on electrical eng. / electronics and communications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.148
H-Index - 7
ISSN - 1685-9545
DOI - 10.37936/ecti-eec.200862.171786
Subject(s) - computer science , cipher , ieee floating point , embedded system , cryptography , computer hardware , computer architecture , floating point , encryption , computer network , operating system , computer security
The key to protect huge amount of multimedia data in ubiquitous networks is to introduce safety aware high-performed single VLSI processor systems embedded with cipher process. Thus, we exploited the architecture of a hardware cryptography embedded multimedia mobile processor named HC-gorilla by sophisticatedly unifying up-to-date processor techniques. Although it was provided with carefully selected Java bytecodes and cipher codes, FP (floating point) expression was omitted due to the restriction of hardware resource. Considering recent trend of embedded applications like voice recognition, 3D graphics, and image/vision processing, FP hardware is crucial for further enhancing HCgorillafs Java functions. We focus in this article the development of a compact FPU (Floating point number Processing Unit). A compact FP format speci¯c for HCgorilla is IEEE 754 compatible except the bit width representation of FP data. Prioritizing the latency of FPU, it has only 5 stages. The compact FPU is built in HCgorilla by adding 16 FP arithmetic codes and improving the decode stage of the previous HCgorilla. By using a 0.18-¹m standard cell CMOS technology supported by VDEC, we have so far accomplished the logic synthesis and behavior simulation. The 400MHz of clock frequency is justified from delay analysis.