RNS based Programmable Decimation Filter for Multi-Standard Wireless Transceivers

Current research on radio frequency transceivers focuses on multi-standard architectures to attain higher system capacities and data rates. Multiple communication standards are made adaptable by performing channel select filtering on chip at baseband in digital domain. The computationally intensive decimation filter in a sigma-delta analog-to-digital converter plays an important role in channel selection for multi-mode systems. As these architectures are targeted for portable applications, an area and power efficient recon¯gurable implementation is animplicit requirement. To this end, a multi-stage, programmable decimation ¯lter based on residue number system (RNS) that is adaptable for WCDMA and WLAN standards is presented in this research. Multi-stage decimation filter implementation offers low computational complexity and power dissipation. The FIR filters of the multi-stage decimator operating in RNS domain offers high data rate because of the carry free operations on smaller residues in parallel channels. Further power saving is achieved by reconfiguring the hardware architecture, and powering down the unused blocks in each mode of operation. For increased programmability modulo multifiplication is performed by index addition utilizing the arithmetic benefits associated with Galois ¯eld. Finally, a performance comparison of the proposed RNS based decimation ¯lter with traditional binary implementation is done in terms of area, critical path delay and power dissipation.