Open AccessRCA on FPGAs Designed by RTL Design Methodology and Wave-Pipelined Operation
Author(s) -
Tomoaki Sato,
Sorawat Chivapreecha,
Phichet Moungnoul,
Kohji Higuchi
Publication year - 2017
Publication title -
ecti transactions on computer and information technology
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.132
H-Index - 2
ISSN - 2286-9131
DOI - 10.37936/ecti-cit.2017111.65680
Subject(s) - field programmable gate array , adder , throughput , computer science , routing (electronic design automation) , embedded system , computer hardware , computer architecture , logic synthesis , parallel computing , logic gate , algorithm , telecommunications , wireless , latency (audio)
Field-programmable gate arrays (FPGAs) are used in various systems with reconfigurable functions. Conventional FPGAs have been developed using a transistor level description for minimizing routing delay. Although FPGAs developed with a register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors advanced their development. They should be shown to operate with practical throughput. For this purpose, circuits on these device need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) was designed and the throughput of the RCA was evaluated. The resulting throughput was applicable to network processors. Additionally, a wave-pipelined operation without changing the RCA revealed that the problem of routing delay in FPGA developed by RTL methodology was mitigated. The contributions of this paper are to clarify that a 4-bit adder can be implemented on FPGAs and their throughput can be improved by wave-pipelined operations.