Open AccessFloating-Point Division Operator based on CORDIC Algorithm
Author(s) -
Pongyupinpanich Surapong,
Faizal Arya Samman
Publication year - 1970
Publication title -
ecti transactions on computer and information technology
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.132
H-Index - 2
ISSN - 2286-9131
DOI - 10.37936/ecti-cit.201371.54356
Subject(s) - cordic , vhdl , division (mathematics) , field programmable gate array , computer science , algorithm , division algorithm , computer hardware , cmos , parallel computing , floating point , arithmetic , electronic engineering , mathematics , engineering
Design and evaluation of a CORDIC (COordinate Rotation DIgital Computer) algorithm for a floatingpoint division operation is presented in this paper. In general, division operation based on CORDIC algorithm has a limitation in term of the range of inputs that can be processed by the CORDIC machine to give proper convergence and precise division operation result. A hardware architecture of CORDIC algorithm capable of processing broader input ranges is implemented and presented in this paper by using a pre-processing and a post-processing stage. The performance as well as the calculation error statistics over exhaustive sets of input tests are evaluated. The results show that the CORDIC algorithm can be well-convergence and gives precise division operation results with broader input ranges. The proposed hardware architecture is modeled in VHDL and synthesized on a CMOS standard-cell technology and a FPGA device, resulting 1 GFlops on the CMOS and 210.812 MFlops on the FPGA device.