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A Cache-based Reconfigurable Accelerator in Die-stacked DRAM
Author(s) -
Yong–Joo Kim
Publication year - 2015
Publication title -
kips transactions on computer and communication systems
Language(s) - Uncategorized
Resource type - Journals
eISSN - 2734-049X
pISSN - 2287-5891
DOI - 10.3745/ktccs.2015.4.2.41
Subject(s) - dram , computer science , cache , overhead (engineering) , embedded system , speedup , stacking , die (integrated circuit) , computer hardware , parallel computing , operating system , physics , nuclear magnetic resonance

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