Open AccessAn Efficient Delay Estimation Model for High Speed VLSI Interconnects
Author(s) -
Kavicharan Mummaneni,
N. S. Murthy,
N. Bheema Rao
Publication year - 2022
Publication title -
wseas transactions on communications/wseas transactions on communications
Language(s) - English
Resource type - Journals
eISSN - 2224-2864
pISSN - 1109-2742
DOI - 10.37394/23204.2022.21.3
Subject(s) - overshoot (microwave communication) , very large scale integration , elmore delay , electronic engineering , interconnection , padé approximant , lossy compression , model order reduction , inductance , propagation delay , computer science , rlc circuit , rational function , control theory (sociology) , mathematics , algorithm , delay calculation , voltage , electrical engineering , engineering , capacitor , telecommunications , mathematical analysis , projection (relational algebra) , control (management) , artificial intelligence
In this paper a closed-form matrix rational model for the computation of step and finite ramp responses of Resistance Inductance Capacitance (RLC) interconnects in VLSI circuits is presented. This model allows the numerical estimation of delay and overshoot in lossy VLSI interconnects. The proposed method is based on the U-transform, which provides rational function approximation for obtaining passive interconnect model. With the reduced order lossy interconnect transfer function, step and finite ramp responses are obtained and line delay and signal overshoot are estimated. The estimated delay and overshoot values are compared with the Euder method, Pade method and HSPICE W- element model. The 50% delay results are in good agreement with those of HSPICE within 0.5% error while the overshoot error is within 1% for a 2 mm long interconnect. For global lines of length more than 5 mm in SOC (system on chip) applications, the proposed method is found to be nearly four times more accurate than existing methods.