Open AccessTrade-off for Leakage Power Reduction in Deep Sub Micron SRAM Design
Author(s) -
Tripti Tripathi,
Durg Singh Chauhan,
Sanjay Kumar Singh
Publication year - 2016
Publication title -
international journal of electrical and electronics research
Language(s) - English
Resource type - Journals
ISSN - 2347-470X
DOI - 10.37391/ijeer.090401
Subject(s) - static random access memory , cache , leakage (economics) , leakage power , cpu cache , cmos , standby power , computer science , embedded system , electronic engineering , engineering , transistor , electrical engineering , computer hardware , parallel computing , voltage , economics , macroeconomics
Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.