Open AccessDouble Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture
Author(s) -
S. Munaf,
A. Bharathi,
A. N. Jayanthi
Publication year - 2016
Publication title -
international journal of electrical and electronics research
Language(s) - English
Resource type - Journals
ISSN - 2347-470X
DOI - 10.37391/ijeer.040103
Subject(s) - control reconfiguration , computer science , embedded system , cache , reduction (mathematics) , field programmable gate array , static random access memory , computer hardware , cas latency , overhead (engineering) , memory architecture , computer architecture , parallel computing , memory controller , operating system , semiconductor memory , geometry , mathematics
Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.