Open AccessComparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits
Author(s) -
Vikas Agarwal,
Shweta Agrawal
Publication year - 2015
Publication title -
international journal of electrical and electronics research
Language(s) - English
Resource type - Journals
ISSN - 2347-470X
DOI - 10.37391/ijeer.030305
Subject(s) - cmos , leakage (economics) , electronic circuit , electronic engineering , cadence , leakage power , logic level , pull up resistor , standby power , logic gate , electrical engineering , voltage , computer science , pass transistor logic , engineering , transistor , digital electronics , economics , macroeconomics
As technology scales in nanometer regime leakage current are becoming important metric of comparable importance to leakage current for the analysis and design of complex logic circuits. In this paper, we did the comparative analysis of leakage current for carry look ahead logic circuits. The simulation results depicts that the proposed design leads to efficient in terms of standby leakage power. We have performed simulations using Cadence Spectra 90nm standard CMOS technology at room temperature with supply voltage of 1V.