Open AccessLeakage current analysis for stack based Nano CMOS Digital Circuits
Author(s) -
Pankaj Agrawal,
Nikhil Saxena
Publication year - 2014
Publication title -
international journal of electrical and electronics research
Language(s) - English
Resource type - Journals
ISSN - 2347-470X
DOI - 10.37391/ijeer.020202
Subject(s) - subthreshold conduction , nmos logic , leakage (economics) , cmos , transistor , standby power , electrical engineering , electronic engineering , mosfet , materials science , drain induced barrier lowering , electronic circuit , engineering , threshold voltage , optoelectronics , voltage , economics , macroeconomics
Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more and more towards the power dissipation in deep submicron Nano CMOS technology. There have been many works on subthreshold leakage and techniques to reduce it, such as controlling the input vector to the circuit in standby mode, forcing stack and body bias control. In this tutorial paper we have reviewed the leakage current with change in drain source, gate and bulk voltages for 4 different submicron technologies using the latest PTM models. Simulation result shows the effect of gate leakage and subthreshold leakage in total leakage current for different input vectors for a stack of 3 Nano technology NMOS transistors, further analyzes also the subthreshold and total leakage variation with input vector in a stack of 4 Nano technology NMOS transistors.