Open AccessEfficient FPGA Implementation of Modular Multiplication and Exponentiation
Author(s) -
M Issad,
M Anane,
B Boudraa,
A M Bellemou,
N Anane
Publication year - 2020
Publication title -
malaysian journal of computing and applied mathematics
Language(s) - English
Resource type - Journals
ISSN - 2636-9400
DOI - 10.37231/myjcam.2020.3.1.37
Subject(s) - modular exponentiation , computer science , field programmable gate array , modular arithmetic , multiplication (music) , modular design , pipeline (software) , embedded system , flexibility (engineering) , microblaze , datapath , parallel computing , exponentiation , computer hardware , arithmetic , public key cryptography , operating system , mathematics , encryption , mathematical analysis , statistics , combinatorics
This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated in Hardware (HW) as Programmable System on Chip (PSoC). The processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between execution time, occupied area and flexibility. In order to satisfy this constraint, Montgomery Power Ladder and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and for the MM implementations as HW accelerators, respectively. Our implementation approach is based on the digit-serial method for performing the basic arithmetic operations. Efficient parallel and pipeline strategies are developed at the digit level for the optimization of the execution time. The application for 1024-bits data length shows that the MMM run in 6.24 µs and requires 647 slices. The ME is executed in 6.75 ms, using 2881 slices.