Design of an Efficient Reverse Converter for Moduli Sets
Author(s) -
Patel Beerendra,
Jitendra Kanungo
Publication year - 2022
Publication title -
journal of engineering research
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.168
H-Index - 9
eISSN - 2307-1885
pISSN - 2307-1877
DOI - 10.36909/jer.icmet.17193
Subject(s) - adder , carry (investment) , arithmetic , computer science , modulo , computer hardware , selection (genetic algorithm) , carry save adder , parallel computing , mathematics , algorithm , telecommunications , discrete mathematics , artificial intelligence , finance , economics , latency (audio)
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