Open AccessLow power and area efficient design of fir filter using enhanced clock gating technique
Author(s) -
L Mohana Kannan,
DHANASKODI DEEPA
Publication year - 2021
Publication title -
journal of engineering research
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.168
H-Index - 9
eISSN - 2307-1885
pISSN - 2307-1877
DOI - 10.36909/jer.11307
Subject(s) - adder , carry save adder , serial binary adder , finite impulse response , very large scale integration , computer science , power–delay product , clock gating , electronic engineering , multiplier (economics) , digital signal processing , arithmetic , computer hardware , algorithm , mathematics , clock signal , cmos , clock skew , engineering , embedded system , telecommunications , jitter , economics , macroeconomics
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