Open AccessFPGA LDPC decoder implementation and optimization its power consumption
Author(s) -
M. Y. Zinchenko,
A. M. Levadniy,
Yu. A. Grebenko,
Mpei
Publication year - 2020
Publication title -
t-comm
Language(s) - English
Resource type - Journals
eISSN - 2072-8743
pISSN - 2072-8735
DOI - 10.36724/2072-8735-2020-14-3-4-10
Subject(s) - low density parity check code , field programmable gate array , computer science , power consumption , parallel computing , power (physics) , computer architecture , soft decision decoder , computer hardware , embedded system , arithmetic , decoding methods , algorithm , mathematics , physics , quantum mechanics