Open AccessValidation of Hybrid Network-on-Chip Architecture for Optimized Performance using BookSim Simulator
Author(s) -
Talla Vamshi,
T. Satya Savithri
Publication year - 2020
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.f8858.038620
Subject(s) - computer science , network on a chip , network simulation , latency (audio) , network architecture , network packet , computer architecture , architecture , system on a chip , chip , computer architecture simulator , embedded system , simulation , distributed computing , computer network , telecommunications , art , visual arts
Various complex integrated circuits suffer from the issues like poor connectivity, higher energy consumption and design productivity. One of the best solutions could be Network-on-Chip architecture which could solve the above issues. The Network-on-Chip architecture should be modelled and simulated well to evaluate the performance and analyse the cost. This paper presents a method to validate the proposed Network-on-Chip architecture with direct sequence spread spectrum using BookSim simulator. This simulation aims at validating the network parameters like packet latency and network latency. The detailed architectural parameters are compared and presented in this paper.