Open AccessDesign and Implementation of Vedic Multiplier
Author(s) -
Akshay Savji,
Shruti Oza
Publication year - 2020
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.f8808.038620
Subject(s) - multiplier (economics) , arithmetic , adder , mathematics , 4 bit , computer science , electronic engineering , cmos , engineering , telecommunications , economics , macroeconomics , latency (audio)
The ancient vedic mathematics has a set of 16 sutras and 13 subsutras. These sutras give suitable method for arithmetic calculations. The vedic formulas requires less time than the regular formulas or method of calculations [1]. Multiplier is an important block in many digital systems. This paper presents a 32-bit vedic multiplier using Urdhva Tiryagbhyam sutra of ancient vedic mathematics. The 32-bit vedic multiplier is implemented using 16-bit multipliers and adders. The 16-bit multipliers are basic blocks in the design by which the input bits are multiplied and their result are added by using the adders. The vedic multiplier can be used in many fast computing processors because of their less time delay and less number of slice LUTs. The result discusses the delay and number of slice LUTs for the implemented 32-bit multiplier. The paper also discusses the methodology of implementation.