Open AccessDesign & Verification of Serial Peripheral Interface (SPI) Protocol
Author(s) -
Polsani Pallavi*,
V. Priyanka,
Dr.Y. Padma Sai
Publication year - 2020
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.f7356.038620
Subject(s) - verilog , computer science , synchronous serial communication , embedded system , interface (matter) , serial communication , computer hardware , protocol (science) , communications protocol , application specific integrated circuit , universal asynchronous receiver/transmitter , chip , serial port , field programmable gate array , computer network , operating system , medicine , telecommunications , alternative medicine , bubble , pathology , maximum bubble pressure method
SPI (Serial Peripheral Interface), which was introduced by the company Motorola, and it is a protocol for communication of serial synchronous about the communication among the master and slave device, which is also used to provide communiqué between microcontroller and many devices which are additional and similar to external Analog to the Digital Converters, Digital to Analog Converters, and EEPROMs. Now a days, communication protocols are at low end. There are two different Protocols: 1) Inter-I2C and 2) SPI. Both of these protocols are well designed for the communications between the Integrated Circuits for communication with On-Board Peripherals. SPI is most commonly used protocol for both intra-chip and inter-chip, and is used at low or medium speed of data-stream transfer. This paper introduces about the quality of SPI Interface Protocol with Single Master and Single Slave configuration, which involves 8-bit of the data transfer and all necessary incorporates features that required for modern applications such as ASIC or SOC (System on Chip). The SPI design is verified and implemented by using System Verilog to show their coverage code and their functional correctness, the entire RTL was written using Verilog for Synthesis and then the Verification architecture is written using System Verilog. The implementation is done using Spartan 3E.