Parallelism Effects in Higher Term Dot Product Floating Point Computation

In complex signal processing applications, Floating Point (FP) arithmetic is a complex, but extremely accurate representation, which needs to be optimizing by architectural modification. This paper describes discrete to fused arithmetic implementation with two, three and four operand FP methodology. Parameters like Area, Power and Delay (APD) are considered for analysis. Exhaustive analysis is carried out here from basic FP component to complete structuring of Four Term Dot Product FP (FTDPFP). Analysis shows that FTDPFP computation improves speed by 89-91% compared to three term and two term computation. Area wise overheads increases in FTDPFP and it is optimized by using new exponent, dual reduction, early normalization, Leading zero participator (LZA), rounding and compounding techniques. Power consumption is optimized with same competency of Two and Three Term Dot Product Floating Point (TTDPFP).