Open AccessPhysical IC Design Layout of Memory-Based Real Fast Fourier Transform Architecture using 90nm Technology
Author(s) -
Rajasekhar Turaka,
D. Janaki Ram
Publication year - 2020
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.e6592.018520
Subject(s) - computer science , asymmetric digital subscriber line , cadence , decimation , application specific integrated circuit , very large scale integration , fast fourier transform , verilog , line code , computer hardware , embedded system , computer architecture , digital subscriber line , electronic engineering , baseband , engineering , algorithm , telecommunications , bandwidth (computing) , field programmable gate array
In this paper we present a low complexity physical IC layout for memory based Real Fast Fourier Transform (RFFT) architecture using 90nm technology. FFT architectures are the most important algorithms in the modern communication systems like and very high bit rate digital subscriber line (VDSL) asymmetric digital subscriber line (ADSL). In this FFT algorithm is based on radix-2 decimation-in-frequency. In order to meet the real time requirements of very large scale integration (VLSI), we designed a low complexity and high speed FFT architecture. The RFFT architecture was realised using Verilog hardware description language (HDL). This architecture is simulated using Native code launch of cadence and synthesized using RTL code complier of cadence tool. Each step of application specific integrated circuit (ASIC) physical IC design flow was synthesized using cadence Innovus 90nm technology and we optimize the design to reduce the area, power and timing requirements