Open AccessLogical Fault Modelling Algorithm for Stuck-at-fault
Author(s) -
K. Mariya Priyadarshini,
Vipul Agarwal,
Ravishankar Ravindran,
K. Mercy Romitha,
Pradeep Kanchan,
Kurra Harshita
Publication year - 2020
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.e4955.018520
Subject(s) - fault coverage , stuck at fault , fault model , fault (geology) , automatic test pattern generation , computer science , fault indicator , fault injection , fault detection and isolation , electronic circuit , algorithm , reliability engineering , engineering , software , electrical engineering , artificial intelligence , seismology , geology , actuator , programming language
With miniaturization happening around with the technology, it’s very important that the faults associated with these circuitsto get accurate results, especially electronics circuits. Besides, finding these faults is a tough job as there will be several test inputs that needs to be tested to check the circuit is fault free or not. Stuck at line is a deficiency prototype used as a part of computerized testing circuit. When any of the line in the circuit is stuck permanently at power supply or ground giving unwanted output, this is called fault. This paper describes about a technique that can be used to find stuck at fault and display the test vectors that generates the faulty output.Any self-assertive different shortcoming in combinational and consecutive circuits can be mimicked and tried utilizing the displayed stuck at fault model. High fault coverage is especially significant during assembling test, and strategies. Stuck at fault results are presented and detected. The outcomes of single stuck at faults are presented in this paper using Verilog code.