Open AccessImplementation of 64-Bits Radix - 8 IFFT for Computation Speed by IDIF using Verilog
Author(s) -
Bipin Kumar,
M. Venkataswamy Reddy,
Vamshi Kollipara,
B. Rajesh
Publication year - 2020
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.e3209.018520
Subject(s) - verilog , computer science , flowchart , decimation , fast fourier transform , radix (gastropod) , computation , inverse , algorithm , arithmetic , computer hardware , mathematics , field programmable gate array , computer network , programming language , botany , geometry , bandwidth (computing) , biology
Always technical designers choice includes algorithms, flowcharts, programming etc and the end users requires given input and application output. Based upon this view this paper focus on the advancement of Inverse Fast Fourier Transform(IFFT) by doing design and observing the performance analysis of 64 point IFFT, using Radix-8 algorithm. The algorithm is developed by Inverse Decimation In Frequency(IDIF) of IFFT, using Verilog as design entity and synthesis are performed in Xilinx. In this architecture the numbers of stages are reduced to 75%.